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april 2011 doc id 18199 rev 3 1/16 16 L6398 high voltage high and low side driver features high voltage rail up to 600 v dv/dt immunity 50 v/ns in full temperature range driver current capability: ? 290 ma source, ? 430 ma sink switching times 75/35 ns rise/fall with 1 nf load 3.3 v, 5 v ttl/cmos input comparators with hysteresis integrated bootstrap diode fixed 320 ns dead-time interlocking function compact and simplified layout bill of material reduction flexible, easy and fast design applications motor driver for home appliances, factory automation, industrial drives and fans. description the L6398 is a high-voltage device manufactured with the bcd ?off-line? tech nology. it is a single chip half-bridge gate driver for n-channel power mosfet or igbt. the high side (floating) section is designed to stand a voltage rail up to 600 v. the logic inputs are cmos/ttl compatible down to 3.3 v for easy interfacing microcontroller/dsp. $)0 3/ table 1. device summary order codes package packaging L6398n dip-8 tube L6398d so-8 tube L6398dtr so-8 tape and reel www.st.com
contents L6398 2/16 doc id 18199 rev 3 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.3 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5.1 ac operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5.2 dc operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 waveforms definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8 bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8.1 cboot selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 9 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
L6398 block diagram doc id 18199 rev 3 3/16 1 block diagram figure 1. block diagram !-v 67 %&5&$5*0/ -&7&- 4)*'5&3 #005453"1%3*7&3 4 7 $$ -7( %3*7&3 7$$ -*/ )*/ )7( %3*7&3 )7( 065 -7 ( #005 67 %&5&$5*0/ 3 -0(*$ 4)005 5)306() 13&7&/5*0/ '-0"5*/(4536$563& gspn-7( ( /% %&"%5*.& 7
pin connection L6398 4/16 doc id 18199 rev 3 2 pin connection figure 2. pin connection (top view) table 2. pin description pin n # pin name type function 1 lin i low side driver logic input (active low) 2 hin i high side driver logic input (active high) 3 vcc p lower section supply voltage 4 gnd p ground 5 lvg (1) 1. the circuit guarantees less than 1 v on the lv g and hvg pins (@ isink = 10 ma), with v cc > 3 v. this allows omitting the ?bleeder? resistor connected bet ween the gate and the source of the external mosfet normally used to hold the pin low. o low side driver output 6 out p high side (floating) common voltage 7 hvg (1) o high side driver output 8 boot p bootstrapped supply voltage !-v 7$$ )*/ 065 )7( (/% -*/ -7( #00 5
L6398 truth table doc id 18199 rev 3 5/16 3 truth table table 3. truth table input output lin hin lvg hvg h l l l l h l l l l h l h h l h
electrical data L6398 6/16 doc id 18199 rev 3 4 electrical data 4.1 absolute maximum ratings note: esd immunity for pins 6, 7 and 8 is guaranteed up to 1 kv (human body model) 4.2 thermal data 4.3 recommended operating conditions table 4. absolute maximum rating symbol parameter value unit min max v cc supply voltage -0.3 21 v v out output voltage v boot - 21 v boot + 0.3 v v boot bootstrap voltage -0.3 620 v v hvg high side gate output voltage v out - 0.3 v boot + 0.3 v v lvg low side gate output voltage -0.3 v cc + 0.3 v v i logic input voltage -0.3 15 v dv out /dt allowed output slew rate 50 v/ns p tot total power dissipation (t a = 25 c) 800 mw t j junction temperature 150 c t stg storage temperature -50 150 c table 5. thermal data symbol parameter so-8 dip-8 unit r th(ja) thermal resistance junction to ambient 150 100 c/w table 6. recommended operating conditions symbol pin parameter test condition min max unit v cc 3supply voltage 1020v v bo (1) 1. v bo = v boot - v out 8-6 floating supply voltage 9.8 20 v v out 6 output voltage - 11 (2) 2. lvg off. vcc = 10 v logic is operational if v boot > 5 v 580 v f sw switching frequency hvg, lvg load c l = 1 nf 800 khz t j junction temperature -40 125 c
L6398 electrical characteristics doc id 18199 rev 3 7/16 5 electrical characteristics 5.1 ac operation figure 3. timing table 7. ac operation electrical characteristics (v cc = 15 v; t j = +25 c) symbol pin parameter test condition min typ max unit t on 1, 2 vs 5, 7 high/low side driver turn-on propagation delay v out = 0 v v boot = vcc c l = 1 nf v in = 0 to 3.3 v see figure 3 50 125 200 ns t off high/low side driver turn-off propagation delay 50 125 200 ns dt dead time (1) c l = 1 nf 225 320 415 ns t r 5, 7 rise time c l = 1 nf 75 120 ns t f fall time c l = 1 nf 35 70 ns 1. see figure 4 on page 9 . hin hvg 50% 10% 90% 50% t r t f t on t off 90% 10% lin lvg 50% 10% 90% 50% t r t f t on t off 90% 10%
electrical characteristics L6398 8/16 doc id 18199 rev 3 5.2 dc operation table 8. dc operation electrical characteristics (v cc = 15 v; t j = + 25 c) symbol pin parameter test condition min typ max unit v cc_hys 3 v cc uv hysteresis 1.2 1.5 1.8 v v cc_thon v cc uv turn on threshold 9 9.5 10 v v cc_thoff v cc uv turn off threshold 7.6 8 8.4 v i qccu undervoltage quiescent supply current v cc = 7 v lin = 5 v; hin = gnd; 90 150 a i qcc quiescent current v cc = 15 v lin = 5 v; hin = gnd; 380 440 a bootstrapped supply voltage section (1) v bo_hys 8 v bo uv hysteresis 0.8 1 1.2 v v bo_thon v bo uv turn on threshold 8.2 9 9.8 v v bo_thoff v bo uv turn off threshold 7.3 8 8.7 v i qbou undervoltage v bo quiescent current v bo = 7 v, lin = hin = 5v 30 60 a i qbo v bo quiescent current v bo = 15 v, lin = hin = 5v 190 240 a i lk high voltage leakage current v hvg = v out = v boot = 600 v 10 a r ds(on) bootstrap driver on resistance (2) lvg o n 1 2 0 driving buffers section i so 5, 7 high/low side source short circuit current v in = v ih (t p < 10 s) 200 290 ma i si high/low side sink short circuit current v in = v il (t p < 10 s) 250 430 ma logic inputs v il 1, 2 low logic level voltage 0.8 v v ih high logic level voltage 2.25 v v il_s 1, 2 single input voltage lin and hin connected together and floating 0.8 v i hinh 2 hin logic ?1? input bias current hin = 15 v 110 175 260 a i hinl hin logic ?0? input bias current hin = 0 v 1 a i linl 1 lin logic ?0? input bias current lin = 0 v 3 6 20 a i linh lin logic ?1? input bias current lin = 15 v 1 a 1. v bo = v boot - v out 2. r dson is tested in the following way: r dson = [(v cc - v cboot1 ) - (v cc - v cboot2 )] / [i 1 (v cc ,v cboot1 ) - i 2 (v cc ,v cboot2 )] where i 1 is pin 8 current when v cboot = v cboot1 , i 2 when v cboot = v cboot2 .
L6398 waveforms definitions doc id 18199 rev 3 9/16 6 waveforms definitions figure 4. dead time and interlocking waveforms definitions lin hin lvg hvg lin hin lvg hvg lin hin lvg hvg lin hin lvg hvg dt lh dt hl dt lh dt hl dt lh dt hl dt lh dt hl gate driver outputs off (half-bridge tri-state) interlocking interlocking control signal edges overlapped: interlocking + dead time control signals edges synchronous (*): dead time control signals edges not overlapped, but inside the dead time: dead time control signals edges not overlapped, outside the dead time: direct driving (*) hin and lin can be connected togheter and driven by just one control signal interlocking interlocking g gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state)
typical application diagram L6398 10/16 doc id 18199 rev 3 7 typical application diagram figure 5. application diagram !-v 67 %&5&$5*0/ -&7&- 4)*'5&3 #00 5453"1%3*7&3 4 7 $$ -7( %3*7&3 7$$ -*/ )* / )7( %3*7&3 )7( 065 -7( #005 67 %&5&$5*0/ 3 -0(*$ 4)00 5 5)306() 13&7&/5*0/ '-0"5*/(4536$563& gspn-7( (/% %&"%5*.& 7 )7 50-0"% $cppu '30.$0/530--&3 '30.$0/530--&3
L6398 bootstrap driver doc id 18199 rev 3 11/16 8 bootstrap driver a bootstrap circuitry is needed to supply the hi gh voltage section. this function is normally accomplished by a high voltage fast recovery diode ( figure 6 ). in the L6398 a patented integrated structure replaces the external diode. it is realized by a high voltage dmos, driven synchronously with the low side driver (lvg), with diode in series, as shown in figure 7 . an internal charge pump ( figure 7 ) provides the dmos driving voltage. 8.1 c boot selection and charging to choose the proper c boot value the external mos can be seen as an equivalent capacitor. this capacitor c ext is related to the mos total gate charge: equation 1 the ratio between the capacitors c ext and c boot is proportional to the cyclical voltage loss. it has to be: equation 2 c boot >>> c ext e.g.: if q gate is 30 nc and v gate is 10 v, c ext is 3 nf. with c boot = 100 nf the drop would be 300 mv. if hvg has to be supplied for a long time, the c boot selection has to take into account also the leakage and quiescent losses. e.g.: hvg steady state consumption is lower than 190 a, so if hvg t on is 5 ms, c boot has to supply 1 c to c ext . this charge on a 1 f capacitor means a voltage drop of 1v. the internal bootstrap driver gives a great advantage: the external fast recovery diode can be avoided (it usually has great leakage current). this structure can work only if v out is close to gnd (or lower) and in the meanwhile the lvg is on. the charging time (t charge ) of the c boot is the time in which both conditions are fulfilled and it has to be long enough to charge the capacitor. the bootstrap driver introduces a voltage drop due to the dmos r dson (typical value: 120 ). at low frequency this drop can be neglected. anyway increasing the frequency it must be taken in to account. the following equation is useful to compute the drop on the bootstrap dmos: equation 3 c ext q gate v gate ------------- - = v drop i ch e arg r dson v drop q gate t ch e arg ------------------ r dson ==
bootstrap driver L6398 12/16 doc id 18199 rev 3 where q gate is the gate charge of the external power mos, r dson is the on resistance of the bootstrap dmos and t charge is the charging time of the bootstrap capacitor. for example: using a power mos with a total gate charge of 30nc the drop on the bootstrap dmos is about 1 v, if the t charge is 5 s. in fact: equation 4 v drop has to be taken into account when the voltage drop on c boot is calculated: if this drop is too high, or the circuit topology doesn?t allo w a sufficient charging time, an external diode can be used. figure 6. bootstrap driver with high voltage fast recovery diode figure 7. bootstrap driver with internal charge pump v drop 30nc 5 s -------------- - 120 0.7v ? = to load h.v. hvg lvg c boot d boot boot v cc out hvg lvg to load h.v. c boot v cc out boot
L6398 package mechanical data doc id 18199 rev 3 13/16 9 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 8. package dimensions table 9. dip-8 mechanical data dim. mm. inch min typ max min typ max a 3.32 0.131 a1 0.51 0.020 b 1.15 1.65 0.045 0.065 b 0.356 0.55 0.014 0.022 b1 0.204 0.304 0.008 0.012 d 10.92 0.430 e 7.95 9.75 0.313 0.384 e 2.54 0.100 e3 7.62 0.300 e4 7.62 0.300 f 6.6 0.260 i 5.08 0.200 l 3.18 3.81 0.125 0.150 z 1.52 0.060
package mechanical data L6398 14/16 doc id 18199 rev 3 table 1. so-8 mechanical data dim. mm. inch min typ max min typ max a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 a2 1.10 1.65 0.043 0.065 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d (1) 1. dimensions d does not include mold flash, protrusions or gate burrs. mold flash, potrusions or gate burrs shall not exceed 0.15mm (.006inc h) in total (both side). 4.80 5.00 0.189 0.197 e 3.80 4.00 0.15 0.157 e 1.27 0.050 h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.40 1.27 0.016 0.050 k 0 (min.), 8 (max.) ddd 0.10 0.004 figure 9. package dimensions
L6398 revision history doc id 18199 rev 3 15/16 10 revision history table 10. document revision history date revision changes 14-dec-2010 1 first release. 16-feb-2011 2 updated ta b l e 8 . 01-apr-2011 3 typo in coverpage
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